A typical Transistor-Transitor Logic (TTL) output circuit or output device for delivering binary logic signals of high or low potential at the signal output OUT is illustrated in FIG. 1. The output device includes a pullup transistor element consisting of the Darlington transistor pair Q5 and Q6 for sourcing current to the signal output OUT from high potential source Vcc and for pulling the output OUT to the logic high level or high potential. The pulldown transistor element Q4 sinks current from the signal output OUT to low potential or ground for establishing a logic low level or low potential signal at the output OUT. The respective conducting states of the pullup and pulldown transistor elements are controlled by the phase-splitter transistor Q3.
When a low level or low potential input signal appears at the signal input IN and input transistor Q1, the phase-splitter base drive current through base drive resistor R1 from high potential source Vcc is diverted and the phase-splitter transistor Q3 is nonconducting. The pulldown transistor Q4 is therefore also nonconducting. Base drive current passes through resistor R3 from potential source Vcc to the base of pullup transistor element Q5, part of the Darlington transistor pair Q5 and Q6. With the pullup transistor element conducting a logic high level or high potential appears at the signal output OUT.
When a high level or high potential signal appears at the signal input iN, then base drive current through resistor R1 is directed to the base of phase-splitter transistor Q3 turning it on. With transistor Q3 conducting the base drive current to the pullup transistor element through resistor R3 is diverted through the collector to emitter of the phase-splitter to the base of the output pulldown transistor Q4. With pulldown transistor Q4 conducting a low level signal or low potential appears at the signal output OUT.
The feedback diode D2 provides a large sink current capability when the output is at high potential for transition at the output from high to low potential. With phase-splitter transistor Q3 conducting the feedback current from the output through diode D2 is amplified by phase-splitter transistor Q3 and applied to the base of pulldown transistor Q4. As hereafter further explained, the increase in output sink current through pulldown transistor Q4 is proportional to .beta..sup.2 during transition from high to low level at the signal output OUT.
As shown in FIG. 1 the typical TTL output device or output circuit with the feedback diode circuit and high current seeking mode is capable of operating only as a bistate device delivering high and low level logic signals at the output for low and high level logic signals appearing at the input. Unlabeled components of the output device of FIG. 1 are typical components well known to those skilled in the art.
Further analysis indicates how the feedback diode D2 enhances the output sink circuit in the prior art TTL output circuit of FIG. 1. When the signal output OUT is at the binary low level or low potential, the output sink current IOL through the collector to emitter circuit of pulldown transistor Q4 is determined by beta, .beta., the gain of the pulldown transistor Q4 and the base current to transistor Q4, IbQ4. EQU IOL=.beta.*IbQ4 (1)
With the signal output OUT at low potential and the phase-splitter transistor Q3 conducting, IbQ4 is in turn the Kirchoff sum of the collector current IcQ3 and the base current IbQ3 through transistor Q3 less the current through squaring network resistor R4, IR4, as follows: EQU IbQ4=IbQ3+IcQ3-IR4 (2)
IcQ3 is in turn the Kirchoff sum of the current through R3, IR3, and the current through D2, ID2. EQU IcQ3=IR3+ID2 (3)
Diode D1 provides a low impedance discharge path for the base of transistor Q6 and the current through diode D1 is neglected because in steady state conditions, it is either reverse biased or conducting substantially less than D2.
If the output voltage Vo is less than the sum of the voltage drop across the base to emitter junction of pulldown transistor Q4, VbeQ4, the voltage drop across the collector to emitter junction of phase-splitter transistor Q3 at saturation, VsatQ3, and the voltage drop across diode D2, VD2, then no feedback current will conduct through diode D2 and the expression for the output sink current IOL through pulldown transistor Q4 is given by: EQU IOL(Vo&lt;VbeQ4+VsatQ3+VD2)=.beta.*(IbQ3+IR3-IR4) (4)
If, however, Vo is greater than VbeQ4+VsatQ3+VD2, then diode D2 will conduct sufficient current to pull the phase-splitter Q3 out of saturation and into the linear operating region. When phase-splitter transistor Q3 is operating in the linear region out of saturation, the collector current IcQ3 becomes: EQU IcQ3=.beta.*IbQ3 (5)
The output sink current IOL through pulldown transistor Q4 therefore becomes: EQU IOL(Vo&gt;VbeQ4+VsatQ3+VD2)=.beta.*((.beta.+1)*IbQ3-IR4) (6)
The difference IOLD in the output sink current IOL between the high and low voltage potentials at the output reduces to: EQU IOLD=.beta..sup.2 *IbQ3-.beta.*IR3 (7)
The difference between the low voltage output sink current capability and the high voltage output sink current capability, that is the step up in the output sink current from low voltage potential to high voltage potential at the output is therefore proportional to .beta..sup.2. By use of the feedback diode D2, the ability of the typical bistate TTL output device to drive large capacity loads or to drive low impedance transmission lines is greatly enhanced without resorting to large increases in base drive to the pulldown transistor Q4 and without increasing the power requirements and power consumption of the output device.
In order to provide a tristate TTL output device capable of establishing a high impedance third state at the signal output OUT for common bus applications, a modification of the TTL output device is required. For example, dual phase-splitter transistors are connected in current mirror configuration as described in U.S. Pat. No. 4,255,670 entitled "Transistor Logic Tristate Output With Feedback". Such a tristate output device with feedback is illustrated in FIG. 2 in which the circuit components which perform the same function as in FIG. 1 are similarly designated. Instead of a single phase splitter transistor Q3 as shown in the bistate output device of FIG. 1, the tristate output device of FIG. 2 includes dual phase-splitter transistors Q2 and Q3 connected in current mirror configuration. In this configuration, the emitters are coupled in parallel to the base of pulldown transistor Q4 for jointly controlling the conducting state of the pulldown transistor element, while the bases of phase-splitter transistors Q2 and Q3 are also tied together at a common terminal at the collector of the input transistor Q1. The collector of the second phase splitter transistor Q2 is coupled through its own collector circuit including collector resistor R2 and diode D3 to the high potential source Vcc.
The tristate output device of FIG. 2 also includes an enable input OE for establishing the high impedance third state. The enable input OE is connected through diode D7 to the base of the pullup transistor element composed of the Darlington pair Q5 and Q6 for disabling the pullup transistor element when a low level or low potential signal appears at the input enable OE. Similarly, the enable input OE is tied through diode D6 to the bases of the dual phase-splitter transistors Q2 and Q3 so that they also are disabled by a low level or low potential signal at the enable input OE. With the phase-splitter transistors nonconducting, the pulldown transistor Q4 is also disabled. With the low level signal at enable input OE, the tristate output device therefore constitutes a high impedance at the signal output OUT and appears or behaves as if it were not there. When a high level signal appears at the enable input OE, the output device operates in the normal bistate mode of operation.
The advantage of the dual phase-splitter transistor elements Q2 and Q3 in combination with the enable input or enable gate is apparent. Only the collector of phase-splitter transistor Q3 is connected to the base of the pullup transistor element for controlling the conducting state of the pullup transistor element. It is the collector of phase-splitter transistor Q3 only that is connected to the enable gate or enable input OE. The collector of phase-splitter transistor Q2 is not connected to the enable gate. Rather, the feedback diode D2 from the signal output OUT and the feedback diode D1 from the base of transistor Q6 are coupled to the collector of phase-splitter transistor Q2. There is no direct coupling therefore between the signal output OUT and the enable gate or enable input OE which would otherwise destroy the high impedance third state. The addition of the second phase-splitter transistor therefore permits the combination of both the feedback diode D2 for accelerated sinking of current from the signal output OUT to ground during the transition at the output from high to low potential, and the enable input OE for establishing the high impedance third state. Furthermore, the blocking diode D3 blocks any current flow from the signal output OUT through the device to the high potential source Vcc.
In summary, the TTL tristate output device with feedback described in U.S. Pat. No. 4,255,670 and illustrated in FIG. 2 provides a plurality of phase-splitter transistors having emitters coupled in parallel for controlling the conducting state of the pulldown transistor element. The collector of a first phase-splitter transistor element is coupled to the base of the pullup transistor element for controllng the conducting state of the pullup transistor element and is also coupled to the enable gate enable input for establishing the high impedance third state. The collector of a second phase-splitter transistor element is coupled to the feedback diode for enhancing the current sinking capability at the signal output OUT by increasing the base drive to the pulldown transistor element. Thus, multiple phase splitter transistors are added with divided functions to combine the tristate enable input and the accelerating feedback diode in the same output device.
A disadvantage attendant upon the combination circuit of FIG. 2, however, is that the full square law enhancement or step-up of the output sink current between the low voltage level and high voltage level at the signal output OUT is lost. The output sink current capability of the multiple phase-splitter transistor TTL tristate output device of FIG. 2 when the multiple phase-splitters are connected in current mirror configuration is as follows. With a high level signal at the signal input IN and a low level signal at the signal output OUT the output sink current IOL through the pulldown transistor Q4 is: EQU IOL=.beta.*IbQ4 (8)
In this instance, however, the base drive current IbQ4 is the Kirchoff sum of the base current from phase-splitter transistor Q2, IbQ2, the collector current through transistor Q2, IcQ2, the base current from phase-splitter transistor Q3, IbQ3, and the collector current from transistor Q3, IcQ3, less the current through squaring network reistor R4, IR4 as follows: EQU IbQ4=IbQ2+IcQ2+IbQ3+IcQ3-IR4 (9)
The collector current through transistor Q2, IcQ2 is in turn the Kirchoff sum of the current through collector resistor R2, IR2 and the feedback current through diode D2, ID2: EQU IcQ2=IR2+ID2 (10)
Again, any current through diode D1 is neglected.
When the output voltage Vo at the signal output OUT is at low potential and less than the voltage drop across the base to emitter junction of pulldown transistor Q4, VbeQ4 plus the voltage drop across the collector to emitter junction of phase-splitter transistor Q2 at saturation, VsatQ2 lus the voltage drop across diode D2, VD2, and therefore no feedback current is flowing from the signal output OUT through diode D2, the output sink current through pulldown transistor Q4 is: EQU IOL(Vo&lt;VbeQ4+VsatQ2+VD2)=.beta.*(IbQ2+IR2+IbQ3+IcQ3-IR4) (11)
When the voltage Vo at signal output OUT is greater than VbeQ4+VsatQ2+VD2, feedback diode D2 becomes forward biased and passes sufficient feedback current from the signal output to pull phase-splitter transistor Q2 out of saturation and into the linear operating range of the transistor. However, because of the current mirror configuration of the phase-splitter transistors Q2 and Q3, as the feedback current through diode D2 to the collector of phase-splitter transistor Q2 is increased, the base current to transistor Q2 decreases. This relationship obtains because in the current mirror configuration the emitter currents of transistors Q2 and Q3 tend to maintain a constant ratio or proportionality according to the ratio of the emitter areas, and in fact tend to remain equal for the example of mirror coupled transistors having equal emitter areas assuming the collector resistors R2 and R3 are equal. This condition may be stated in the following equation. EQU IbQ2+IR2+ID2=IbQ3+IcQ3 (12)
There is also the additional restraint that: EQU IbQ2+IbQ3=IR1 (13)
When the feedback diode D2 is nonconducting and ID2 equals 0, the collector currents and base currents of the phase-splitter transistors Q2 and Q3 are respectively matched with each other according to the following equalities assuming by way of example that the emitter areas are equal and resistor R2 equals R3: EQU IcQ2=IR2=IcQ3=IR3 (14) EQU IbQ2=IbQ3=IR1/2 (15)
With the output voltage Vo at a sufficient level so that feedback diode D2 is conducting, the feedback current ID2 necessary to force phase-splitter transistor Q2 out of saturation and into the linear operating region is: EQU ID2=IbQ3+IcQ3-IbQ2-IR2 EQU ID2=(IbQ3+IcQ3)*(.beta.*1/(.beta.+1))-IR2 EQU ID2=IcQ3+IbQ3-IR2 EQU ID2=IcQ3+IR1-IR2 (16)
With this level of feedback current as set forth in equation (16), the phase-splitter transistor Q2 operates just on the edge of its linear operating range while phase-splitter transistor Q3 is saturated, "hogging" essentially all of the base drive current IR1 through resistor R1. In equation (16) the 1/.beta. term has been disregarded and dropped as being negligible compared to 1 for reasonable values of .beta..
Substituting equations (15), (13), (10) and (9) into equation (8) yields the following expression for the output sink current IOL when a low voltage level signal is applied at the output OUT. EQU IOL(Vo&gt;VbeQ4+VsatQ2+VD2)=.beta.*(2*(IcQ3+IR1)-IR4) (17)
Substituting equation (13) into equation (11) yields the following expression for the output sink current IOL for a high voltage level signal at the output OUT: EQU IOL(Vo&lt;VbeQ4+VsatQ2+VD2)=.beta.*(IcQ3+IR1+IR2-IR4) (18)
Comparing and subtracting equations (17) and (18) gives the following current difference IOLD between the output sink current IOL with low potential at the output and the output sink current IOL with high level potential at the output. EQU IOLD=.beta.*(IcQ3+IR1-IR2) (19)
Noting that the dual phase-splitter transistors Q2 and Q3 are coupled in current mirror configuration so that the collector and base currents are matched when the feedback current ID2 is 0, equation (14) may be substituted into equation (19) giving the following expression for the difference current or step IOLD in the output sink current between the low and high level potentials at the output OUT: EQU IOLD=.beta.*(IR1) (20)
From this expression it is noted that the difference between the low voltage output current sink capability and the high voltage output current sink capability, here referred to as the gain "step" or gain "step-up" in the output sink current is here proportional to .beta. for the tristate output device of FIG. 2 as compared with the gain step-up proportional to .beta..sup.2 for the bistate output device of FIG. 1. This is unfortunate because the high current sink mode afforded by the gain step-up proportional to .beta..sup.2 is even more important and desirable for the tristate output devices than it is for the bistate output devices. This is because the tristate output devices are generally connected to long signal buses or common buses which are generally of lower impedance and are more capacitive. According to the prior art output devices, however, the combination of the desirable component configurations with enable gate input and feedback diodes using dual or multiple phase-splitter transistors results in a gain step-up for the current sinking capability between low level potential and high level potential at the output proportional to .beta. only and not .beta..sup.2 with consequent loss of the high current sinking mode and loss of the gain step-up proportional to .beta..sup.2 achieved in the bistate output devices.